🏆 Chip Design LLM Zoo 🏆
———— Verilog Leaderboard ————
📝 Notes
- Evaluated using VerilogEval; RTLLM version 1.0; RTLLM version 1.1;.
- Models are ranked according to pass@1 in VerilogEval and correct rate in RTLLM.
- ✨ marks the finetuning LLMs, while others perform LLMs without finetuning.
- Model providers have the responsibility to avoid data contamination. Models trained on close data can be affected by contamination.
- 💚 means open weights and open data. 💙 means open weights.
- "Size" here is the amount of activated model weight during inference.
- The test result data comes from their papers. The test results in each paper may have different settings.
🙏 Acknowledgements
- We thank the EvalPlus team for providing the leaderboard template.
- We are grateful for the significant contributions to the Awesome Chip Design Leader Board.