🏆 Chip Design LLM Zoo 🏆

———— Verilog Leaderboard ————

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📝 Notes

  1. Evaluated using VerilogEval; RTLLM version 1.0; RTLLM version 1.1;.
  2. Models are ranked according to pass@1 in VerilogEval and correct rate in RTLLM.
  3. ✨ marks the finetuning LLMs, while others perform LLMs without finetuning.
  4. Model providers have the responsibility to avoid data contamination. Models trained on close data can be affected by contamination.
  5. 💚 means open weights and open data. 💙 means open weights.
  6. "Size" here is the amount of activated model weight during inference.
  7. The test result data comes from their papers. The test results in each paper may have different settings.

🙏 Acknowledgements

  • We thank the EvalPlus team for providing the leaderboard template.
  • We are grateful for the significant contributions to the Awesome Chip Design Leader Board.